This invention relates to the field of data processing; and more particularly, it relates to methods of routing a message through an array of data processing nodes such that the message can be distributed to many nodes at scattered locations very quickly.
As used herein, the term data processing node is meant to include the combination of at least the following items: a microprocessor chip, a memory coupled to the microprocessor chip, and an input-output channel for external data transfers to and from the microprocessor chip. Here, the microprocessor/memory/input-output channel can have any internal make-up.
A single data processing node has use by itself in that the memory can store a program for the microprocessor chip to execute, and data on which the program operates can be sent to the data processing node via the input-output channel. However, when a plurality data processing nodes are intercoupled together in an array, several advantages over a single data processing node are achieved.
Such an array is formed by providing with each data processing node, a respective message routing circuit which has multiple input-output channels. Then in the actual array, the input-output channels of the message routing circuits and data processing nodes are all intercoupled together. This array is herein referred to as a parallel processor.
One advantage of the above parallel processor is that it provides a selectable or scalable amount of computing power. To increase/decrease its computing power, some data processing nodes are simply added to/deleted from the array. Another advantage of the above parallel processor is that it provides computing power which is fail-soft. This means that one or more data processing nodes can fail and be in need of repair, while the remaining nodes in the array continue to operate.
However, the overall performance of the above parallel processor is greatly affected by the process by which a message is routed from one source node S to many receiving nodes R at scattered locations in the array. Such a message can, for example, specify a task for each receiving node to perform. If the time that it takes for all of the receiving nodes to receive their respective tasks is reduced, then the time that it takes for all of the receiving nodes to complete those tasks will likewise be reduced.
Presently in the art, Intel Corporation sells a parallel processor, called the "Paragon", which comprises a plurality of data processing nodes that are intercoupled in an array through respective message routing circuits. However, a major drawback with the Paragon is that each message which travels through the array can only be sent from one source node S to one receiving node R. That is, each message has a point-to-point route. Consequently, in order to send a message from one source node to many receiving nodes, a series of point-to-point messages need to be sent; and, establishing the corresponding series of point-to-point routes consumes a large amount of time.
Accordingly, a primary object of the invention is to provide an improved method of routing messages through an array of data processing nodes whereby the above drawback is overcome.